All programsAenexz Tech
Dual Certified
4.9
VLSI Physical Design
Synopsys, Cadence Innovus, OpenLANE and Sky130 PDK — floorplan, placement, CTS, routing, STA and signoff with 10+ micro-projects and a live RTL-to-GDSII project.
Duration
8 Weeks
Level
Beginner → Intermediate
Prerequisites
Basic Electronics Knowledge
Curriculum
Week 11 Week
VLSI Foundations
Digital electronics, MOSFET, CMOS basics, Linux and TCL intro.
- Digital electronics revision — logic gates and flip-flops
- MOSFET operation and CMOS inverter
- VLSI design flow overview
- Linux command line for VLSI engineers
- TCL scripting fundamentals
Week 21 Week
ASIC Flow, Synthesis, STA & Floorplan
From RTL to floorplan with industry EDA tools.
- ASIC design flow: RTL → GDSII
- Logic synthesis fundamentals with Synopsys DC
- Timing constraints (SDC): create_clock, set_input_delay
- Static Timing Analysis (STA) basics
- Floorplanning: core area, IO placement, macro placement, power rings & power grid design
Week 31 Week
Placement, CTS & Routing
Physical implementation with optimisation.
- Standard cell placement and optimisation
- Congestion analysis
- Clock Tree Synthesis (CTS) — skew and latency
- Routing: global, detailed, DRC-clean nets
- Signal integrity, crosstalk, antenna effects & via optimization
Week 41 Week
Signoff & Interview Prep
Timing closure, signoff checks and job readiness.
- Timing closure: setup and hold fixes
- Multi-corner signoff & MMMC timing with PrimeTime
- IR drop, electromigration & antenna checks
- Physical verification: DRC, LVS, ERC
- TCL scripting & automation for Synopsys / Innovus / OpenLANE flows
- Full ASIC flow revision + interview coaching
Week 5–84 Weeks
Live RTL2GDSII Project
Real block-level implementation with mentors.
- Onboarding to live RTL2GDSII project
- Align goals with expert mentors
- Weekly code reviews and feedback
- Deliverables review with industry partners
- Final showcase — Dual Certificate (Internship + Freelancer)
Tools & Technologies
Synopsys Design CompilerSynopsys PrimeTimeCadence InnovusOpenLANESky130 PDKLinuxTCLGitMagic VLSI
Capstone Projects
Capstone
RTL-to-GDSII Implementation on Sky130
Micro
